The use of error correcting codes is now widespread in memory systems. They are intended to correct defects occurring in the manufacture of circuits by supplementing or replacing the traditional redundancy columns, and to correct defects occurring during the operation of the memory.
For example, dynamic memory circuits (DRAMs) increasingly comprise error correcting code blocks to increase manufacturing yields or to correct errors produced from the alpha particles bombardment that occurs during the life of the product. Nonvolatile memories of the flash/EEPROM type are also increasingly associating their control circuits with error correcting systems, such as in the field of multi-level/bit memories, to increase the data retention characteristics and the reliability of the circuits. Generally, in these applications, the coded data are read and processed by a decoder which provides an indication of the presence of errors and their number, and possibly corrects them, or indicates that correction is not possible.
The complexity of coders/decoders varies from one system to another, but most use the principle of reading and analysis. The correcting circuits used most often in the field of memories make use of Hamming or Reed-Solomon (RS) type linear codes belonging to the family of Bose-Chaudhuri-Hocquenghem (BCH) codes. These codes are characterized by the length of their code blocks. More precisely, these code blocks comprise k data containing the useful information item and r control bits, the sum k+r being equal to n and defining the length of the code block.
The evaluation of the characteristics of the corrector blocks must consider the increase in area introduced by the cells storing the control bits, the area occupied by the coders/decoders, and the delays produced by the passage of the data through these blocks which penalize the memory access times. The integration of the correcting circuits then usually results from a compromise made between these various criteria and the gain in reliability, which does not generally make it possible to integrate overly complex codes.
Industrial fabrication is therefore now gearing towards the integration of codes making it possible to correct an error and to detect two errors. Such detecting and correcting codes are for example those called “SEC-DED” (“Single Error Correction-Double Error Detection”) codes. An example of such codes is described in U.S. Pat. No. 3,623,155 to Hsiao et al.
Other codes, of the cyclic redundancy type (CRC: Cyclic Redundancy Code), may sometimes be used. These codes rely on the principle of polynomial division. More precisely, the binary information item to be coded is regarded as a polynomial which, once divided by a definite number, gives a remainder which is coded by the control bits. The best known characteristic polynomials are the CRC16-forward (x16+x15+x2+1) and the CRC-CCITT (x16+x12+x5+1). Although these codes are simple and exhibit a low overhead of area, their drawback is that they only constitute error detection codes and do not perform corrections. Thus, they are intended to be employed for testing memories, which use a specific test circuit integrated during the manufacture of the memory, using an associated test algorithm (known by the person skilled in the art by the name “BIST: Built-In-Self-Test”).
In systems using correcting codes of the SEC-DED type, if the number of errors exceeds unity, then correction is not possible and the information item contained in the memory remains erroneous. Moreover, if the number of errors is greater than two, the system is no longer capable of detecting the errors and then provides a false information item. This principle of error detection-correction is well suited to cases for which the errors are due to the deficiency of isolated bits, but is inadequate when the errors originate from a more global drifting of the characteristics of the memory cells or slots.
Additionally, cyclic redundancy codes (of the CRC type), although efficient for error detection, are currently restricted to the field of testing (BIST) in which a single information item, of the “good or bad circuit” type, is sought. These systems therefore appear to be limited and not very robust for use where the degradation of data in a memory occurs during the life of the product.
A few attempts to improve the systems are currently reported in the literature. More precisely, some use a read only memory, such as U.S. Pat. No. 4,163,147 to Greive et al. Other attempts introduce the possibility of correcting two errors with an error correcting code of the SEC-DED type, but only if one of the two errors is a hardware error (hard error), such as in U.S. Pat. No. 4,319,357 to Bossen. Additionally, U.S. Pat. No. 6,657,896 to Hosono et al. proposes a complex circuit for coding a current that is proportional to the number of 1's contained in the information words.